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Rev Log message Author Age Path
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 8125d 22h /ethmac/tags/rel_24/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 8125d 22h /ethmac/tags/rel_24/
238 Defines fixed to use generic RAM by default. mohor 8138d 02h /ethmac/tags/rel_24/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 8140d 07h /ethmac/tags/rel_24/
235 rev 4. mohor 8140d 22h /ethmac/tags/rel_24/
234 Figure list assed to the revision 3. mohor 8141d 06h /ethmac/tags/rel_24/
233 Revision 0.3 released. Some figures added. mohor 8141d 06h /ethmac/tags/rel_24/
232 fpga define added. mohor 8146d 01h /ethmac/tags/rel_24/
231 Description of Core Modules added (figure). mohor 8148d 03h /ethmac/tags/rel_24/
229 case changed to casex. mohor 8151d 23h /ethmac/tags/rel_24/
227 Changed BIST scan signals. tadejm 8152d 03h /ethmac/tags/rel_24/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 8152d 05h /ethmac/tags/rel_24/
225 Some minor changes. tadejm 8152d 05h /ethmac/tags/rel_24/
224 Signals for a wave window in Modelsim. tadejm 8152d 06h /ethmac/tags/rel_24/
223 Some code changed due to bug fixes. tadejm 8152d 06h /ethmac/tags/rel_24/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 8156d 04h /ethmac/tags/rel_24/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 8159d 05h /ethmac/tags/rel_24/
218 Typo error fixed. (When using Bist) mohor 8159d 07h /ethmac/tags/rel_24/
217 Bist supported. mohor 8159d 07h /ethmac/tags/rel_24/
216 Bist signals added. mohor 8159d 07h /ethmac/tags/rel_24/
215 Bist supported. mohor 8159d 08h /ethmac/tags/rel_24/
214 Signals for WISHBONE B3 compliant interface added. mohor 8160d 03h /ethmac/tags/rel_24/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 8160d 03h /ethmac/tags/rel_24/
212 Minor $display change. mohor 8160d 04h /ethmac/tags/rel_24/
211 Bist added. mohor 8160d 04h /ethmac/tags/rel_24/
210 BIST added. mohor 8160d 04h /ethmac/tags/rel_24/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 8161d 07h /ethmac/tags/rel_24/
208 Virtual Silicon RAMs moved to lib directory tadej 8177d 01h /ethmac/tags/rel_24/
207 Virtual Silicon RAM support fixed tadej 8177d 01h /ethmac/tags/rel_24/
206 Virtual Silicon RAM added to the simulation. mohor 8177d 01h /ethmac/tags/rel_24/

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