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[/] [ethmac/] [tags/] [rel_24/] [rtl/] - Rev 250

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Rev	Log message	Author	Age	Path
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7821d 05h	/ethmac/tags/rel_24/rtl/
248	wb_rst_i is used for MIIM reset.	mohor	7822d 05h	/ethmac/tags/rel_24/rtl/
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	7825d 08h	/ethmac/tags/rel_24/rtl/
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7826d 04h	/ethmac/tags/rel_24/rtl/
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7827d 00h	/ethmac/tags/rel_24/rtl/
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	7827d 00h	/ethmac/tags/rel_24/rtl/
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7827d 00h	/ethmac/tags/rel_24/rtl/
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7827d 01h	/ethmac/tags/rel_24/rtl/
238	Defines fixed to use generic RAM by default.	mohor	7839d 05h	/ethmac/tags/rel_24/rtl/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7841d 10h	/ethmac/tags/rel_24/rtl/
232	fpga define added.	mohor	7847d 04h	/ethmac/tags/rel_24/rtl/
229	case changed to casex.	mohor	7853d 02h	/ethmac/tags/rel_24/rtl/
227	Changed BIST scan signals.	tadejm	7853d 06h	/ethmac/tags/rel_24/rtl/
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7853d 07h	/ethmac/tags/rel_24/rtl/
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7857d 07h	/ethmac/tags/rel_24/rtl/
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7860d 07h	/ethmac/tags/rel_24/rtl/
218	Typo error fixed. (When using Bist)	mohor	7860d 09h	/ethmac/tags/rel_24/rtl/
214	Signals for WISHBONE B3 compliant interface added.	mohor	7861d 06h	/ethmac/tags/rel_24/rtl/
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7861d 06h	/ethmac/tags/rel_24/rtl/
212	Minor $display change.	mohor	7861d 06h	/ethmac/tags/rel_24/rtl/

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[/] [ethmac/] [tags/] [rel_24/] [rtl/] - Rev 250

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