URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_24/] [rtl/] - Rev 304

Rev	Log message	Author	Age	Path
257	When TxUsedData and CtrlMux occur at the same time, byte counter needs to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.	mohor	7819d 19h	/ethmac/tags/rel_24/rtl/
256	TxDone and TxAbort changed so they're not propagated to the wishbone module when control frame is transmitted.	mohor	7819d 19h	/ethmac/tags/rel_24/rtl/
255	TPauseRq synchronized to tx_clk.	mohor	7819d 19h	/ethmac/tags/rel_24/rtl/
253	r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.	mohor	7821d 01h	/ethmac/tags/rel_24/rtl/
251	When control frame (PAUSE) was sent, status was written in the eth_wishbone module and both TXB and TXC interrupts were set. Fixed. Only TXC interrupt is set.	mohor	7821d 02h	/ethmac/tags/rel_24/rtl/
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7821d 02h	/ethmac/tags/rel_24/rtl/
248	wb_rst_i is used for MIIM reset.	mohor	7822d 02h	/ethmac/tags/rel_24/rtl/
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	7825d 05h	/ethmac/tags/rel_24/rtl/
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7826d 01h	/ethmac/tags/rel_24/rtl/
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7826d 21h	/ethmac/tags/rel_24/rtl/