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[/] [ethmac/] [tags/] [rel_24/] [rtl/] [verilog/] [eth_spram_256x32.v] - Rev 338

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Rev Log message Author Age Path
338 root 5441d 06h /ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
335 New directory structure. root 5498d 11h /ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
307 This commit was manufactured by cvs2svn to create tag 'rel_24'. 7420d 06h /ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
306 Lapsus fixed (!we -> ~we). simons 7420d 06h /ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7442d 03h /ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
302 mbist signals updated according to newest convention markom 7468d 13h /ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
297 Artisan ram instance added. simons 7532d 04h /ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
227 Changed BIST scan signals. tadejm 7832d 04h /ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
210 BIST added. mohor 7840d 05h /ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7857d 03h /ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7919d 04h /ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v

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