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[/] [ethmac/] [tags/] [rel_24/] [sim/] - Rev 350


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Rev Log message Author Age Path
338 root 4847d 05h /ethmac/tags/rel_24/sim
335 New directory structure. root 4904d 10h /ethmac/tags/rel_24/sim
307 This commit was manufactured by cvs2svn to create tag 'rel_24'. 6826d 05h /ethmac/tags/rel_24/sim
299 Artisan RAMs added. mohor 6932d 08h /ethmac/tags/rel_24/sim
295 Few minor changes. tadejm 6939d 07h /ethmac/tags/rel_24/sim
294 Added path to a file with distributed RAM instances for xilinx. tadejm 6941d 07h /ethmac/tags/rel_24/sim
293 initial. tadejm 6965d 04h /ethmac/tags/rel_24/sim
292 Corrected mistake. tadejm 6965d 04h /ethmac/tags/rel_24/sim
291 initial tadejm 6965d 06h /ethmac/tags/rel_24/sim
290 Additional checking for FAILED tests added - for ATS. tadejm 6965d 07h /ethmac/tags/rel_24/sim
225 Some minor changes. tadejm 7238d 05h /ethmac/tags/rel_24/sim
224 Signals for a wave window in Modelsim. tadejm 7238d 06h /ethmac/tags/rel_24/sim
217 Bist supported. mohor 7245d 07h /ethmac/tags/rel_24/sim
215 Bist supported. mohor 7245d 08h /ethmac/tags/rel_24/sim
208 Virtual Silicon RAMs moved to lib directory tadej 7263d 01h /ethmac/tags/rel_24/sim
207 Virtual Silicon RAM support fixed tadej 7263d 01h /ethmac/tags/rel_24/sim
206 Virtual Silicon RAM added to the simulation. mohor 7263d 01h /ethmac/tags/rel_24/sim
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7263d 02h /ethmac/tags/rel_24/sim
187 _info file added. mohor 7269d 01h /ethmac/tags/rel_24/sim
186 Macro for testbench (DO file). mohor 7269d 01h /ethmac/tags/rel_24/sim

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