OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_25/] - Rev 130

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
130 First draft of the Ethernet design document. Not a finished version. Still many
things missing.
mohor 8155d 16h /ethmac/tags/rel_25/
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
interfaces:
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 8155d 17h /ethmac/tags/rel_25/
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 8175d 16h /ethmac/tags/rel_25/
126 InvalidSymbol generation changed. mohor 8175d 16h /ethmac/tags/rel_25/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 8175d 16h /ethmac/tags/rel_25/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 8175d 17h /ethmac/tags/rel_25/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 8177d 18h /ethmac/tags/rel_25/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 8177d 18h /ethmac/tags/rel_25/
120 Unused files removed. mohor 8177d 19h /ethmac/tags/rel_25/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 8177d 19h /ethmac/tags/rel_25/
118 ShiftEnded synchronization changed. mohor 8181d 10h /ethmac/tags/rel_25/
117 Clock mrx_clk set to 2.5 MHz. mohor 8181d 20h /ethmac/tags/rel_25/
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 8181d 20h /ethmac/tags/rel_25/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 8182d 18h /ethmac/tags/rel_25/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 8183d 16h /ethmac/tags/rel_25/
113 RxPointer bug fixed. mohor 8190d 07h /ethmac/tags/rel_25/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8190d 21h /ethmac/tags/rel_25/
111 Master state machine had a bug when switching from master write to
master read.
mohor 8191d 10h /ethmac/tags/rel_25/
110 m_wb_cyc_o signal released after every single transfer. mohor 8191d 14h /ethmac/tags/rel_25/
109 Comment removed. mohor 8191d 14h /ethmac/tags/rel_25/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.