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154 Design document is still under construction. mohor 6707d 12h /ethmac/tags/rel_25/
153 Temp version (backup). mohor 6708d 03h /ethmac/tags/rel_25/
152 Version 1.16 created. See revision history in the document for details. mohor 6708d 04h /ethmac/tags/rel_25/
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.
mohor 6708d 05h /ethmac/tags/rel_25/
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
mohor 6708d 05h /ethmac/tags/rel_25/
148 Bug when last byte of destination address was not checked fixed. mohor 6708d 05h /ethmac/tags/rel_25/
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.
mohor 6708d 05h /ethmac/tags/rel_25/
146 CarrierSenseLost status is not set when working in loopback mode. mohor 6708d 05h /ethmac/tags/rel_25/
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 6708d 05h /ethmac/tags/rel_25/
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
mohor 6724d 08h /ethmac/tags/rel_25/
141 Syntax error fixed. mohor 6727d 01h /ethmac/tags/rel_25/
140 Syntax error fixed. mohor 6727d 01h /ethmac/tags/rel_25/
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 6727d 02h /ethmac/tags/rel_25/
138 Synchronous reset added. mohor 6727d 02h /ethmac/tags/rel_25/
137 Defines for register width added. mii_rst signal in MIIMODER register
mohor 6727d 02h /ethmac/tags/rel_25/
136 Parameter ResetValue changed to capital letters. mohor 6727d 11h /ethmac/tags/rel_25/
135 New revision. External DMA removed, TX_BD_NUM changed. mohor 6729d 03h /ethmac/tags/rel_25/
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 6729d 04h /ethmac/tags/rel_25/
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).
mohor 6729d 05h /ethmac/tags/rel_25/
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 6729d 05h /ethmac/tags/rel_25/
131 LinkFail signal was not latching appropriate bit. mohor 6729d 06h /ethmac/tags/rel_25/
130 First draft of the Ethernet design document. Not a finished version. Still many
things missing.
mohor 6729d 06h /ethmac/tags/rel_25/
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 6729d 07h /ethmac/tags/rel_25/
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 6749d 05h /ethmac/tags/rel_25/
126 InvalidSymbol generation changed. mohor 6749d 06h /ethmac/tags/rel_25/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
mohor 6749d 06h /ethmac/tags/rel_25/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 6749d 07h /ethmac/tags/rel_25/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 6751d 07h /ethmac/tags/rel_25/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 6751d 07h /ethmac/tags/rel_25/
120 Unused files removed. mohor 6751d 08h /ethmac/tags/rel_25/

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