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131 LinkFail signal was not latching appropriate bit. mohor 6729d 05h /ethmac/tags/rel_25/
130 First draft of the Ethernet design document. Not a finished version. Still many
things missing.
mohor 6729d 06h /ethmac/tags/rel_25/
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
interfaces:
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 6729d 07h /ethmac/tags/rel_25/
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 6749d 05h /ethmac/tags/rel_25/
126 InvalidSymbol generation changed. mohor 6749d 05h /ethmac/tags/rel_25/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 6749d 06h /ethmac/tags/rel_25/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 6749d 06h /ethmac/tags/rel_25/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 6751d 07h /ethmac/tags/rel_25/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 6751d 07h /ethmac/tags/rel_25/
120 Unused files removed. mohor 6751d 08h /ethmac/tags/rel_25/

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