OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_25/] [bench/] - Rev 180

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
180 Bench outputs data to display every 128 bytes. mohor 7867d 20h /ethmac/tags/rel_25/bench/
179 Beautiful tests merget together mohor 7867d 20h /ethmac/tags/rel_25/bench/
178 Rearanged testcases mohor 7867d 20h /ethmac/tags/rel_25/bench/
177 Bug in MIIM fixed. mohor 7868d 00h /ethmac/tags/rel_25/bench/
170 Headers changed. mohor 7868d 03h /ethmac/tags/rel_25/bench/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7868d 03h /ethmac/tags/rel_25/bench/
158 Typo fixed. mohor 7872d 23h /ethmac/tags/rel_25/bench/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7875d 04h /ethmac/tags/rel_25/bench/
156 Valid testbench. mohor 7875d 04h /ethmac/tags/rel_25/bench/
155 Minor changes. mohor 7875d 04h /ethmac/tags/rel_25/bench/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7917d 22h /ethmac/tags/rel_25/bench/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7919d 23h /ethmac/tags/rel_25/bench/
117 Clock mrx_clk set to 2.5 MHz. mohor 7924d 01h /ethmac/tags/rel_25/bench/
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 7924d 01h /ethmac/tags/rel_25/bench/
108 Testbench supports unaligned accesses. mohor 8001d 05h /ethmac/tags/rel_25/bench/
107 TX_BUF_BASE changed. mohor 8001d 05h /ethmac/tags/rel_25/bench/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 8046d 02h /ethmac/tags/rel_25/bench/
80 Small fixes for external/internal DMA missmatches. mohor 8066d 22h /ethmac/tags/rel_25/bench/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8077d 02h /ethmac/tags/rel_25/bench/
66 Testbench fixed, code simplified, unused signals removed. mohor 8077d 08h /ethmac/tags/rel_25/bench/
51 Added separate tests for Multicast, Unicast, Broadcast billditt 8078d 19h /ethmac/tags/rel_25/bench/
49 HASH0 and HASH1 register read/write added. mohor 8080d 19h /ethmac/tags/rel_25/bench/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8087d 01h /ethmac/tags/rel_25/bench/
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8147d 03h /ethmac/tags/rel_25/bench/
23 Number of addresses (wb_adr_i) minimized. mohor 8197d 04h /ethmac/tags/rel_25/bench/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 8197d 06h /ethmac/tags/rel_25/bench/
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 8222d 00h /ethmac/tags/rel_25/bench/
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8262d 01h /ethmac/tags/rel_25/bench/
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 8271d 00h /ethmac/tags/rel_25/bench/
12 Directory structure changed. Files checked and joind together. mohor 8277d 17h /ethmac/tags/rel_25/bench/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.