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[/] [ethmac/] [tags/] [rel_25/] [bench/] [verilog/] [tb_ethernet.v] - Rev 338

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Rev Log message Author Age Path
338 root 5466d 20h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
335 New directory structure. root 5524d 01h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
316 This commit was manufactured by cvs2svn to create tag 'rel_25'. 7444d 22h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
315 Updated testbench. Some more testcases, some repaired. tadejm 7444d 22h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
302 mbist signals updated according to newest convention markom 7494d 03h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
299 Artisan RAMs added. mohor 7551d 23h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7752d 19h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
279 Underrun test fixed. Many other tests fixed. mohor 7753d 22h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
274 Backup version. Not fully working. tadejm 7761d 16h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
267 Full duplex control frames tested. mohor 7817d 19h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
266 Flow control test almost finished. mohor 7822d 18h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7823d 09h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7823d 21h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
254 Temp version. mohor 7825d 15h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
252 Just some updates. tadejm 7825d 18h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
243 Late collision is not reported any more. tadejm 7830d 22h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
227 Changed BIST scan signals. tadejm 7857d 18h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
223 Some code changed due to bug fixes. tadejm 7857d 21h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7866d 22h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
194 Full duplex tests modified and testbench bug repaired. tadej 7885d 21h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v

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