OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_26/] - Rev 281

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
mohor 7825d 03h /ethmac/tags/rel_26/
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.
mohor 7825d 03h /ethmac/tags/rel_26/
255 TPauseRq synchronized to tx_clk. mohor 7825d 03h /ethmac/tags/rel_26/
254 Temp version. mohor 7826d 06h /ethmac/tags/rel_26/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7826d 09h /ethmac/tags/rel_26/
252 Just some updates. tadejm 7826d 09h /ethmac/tags/rel_26/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 7826d 09h /ethmac/tags/rel_26/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7826d 09h /ethmac/tags/rel_26/
248 wb_rst_i is used for MIIM reset. mohor 7827d 09h /ethmac/tags/rel_26/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7830d 12h /ethmac/tags/rel_26/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.