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[/] [ethmac/] [tags/] [rel_26/] [bench/] [verilog/] - Rev 338

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Rev Log message Author Age Path
338 root 5467d 20h /ethmac/tags/rel_26/bench/verilog/
335 New directory structure. root 5525d 01h /ethmac/tags/rel_26/bench/verilog/
322 This commit was manufactured by cvs2svn to create tag 'rel_26'. 7302d 20h /ethmac/tags/rel_26/bench/verilog/
318 Latest Ethernet IP core testbench. tadejm 7333d 19h /ethmac/tags/rel_26/bench/verilog/
315 Updated testbench. Some more testcases, some repaired. tadejm 7445d 22h /ethmac/tags/rel_26/bench/verilog/
302 mbist signals updated according to newest convention markom 7495d 03h /ethmac/tags/rel_26/bench/verilog/
299 Artisan RAMs added. mohor 7552d 23h /ethmac/tags/rel_26/bench/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7620d 23h /ethmac/tags/rel_26/bench/verilog/
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7753d 19h /ethmac/tags/rel_26/bench/verilog/
279 Underrun test fixed. Many other tests fixed. mohor 7754d 22h /ethmac/tags/rel_26/bench/verilog/
274 Backup version. Not fully working. tadejm 7762d 16h /ethmac/tags/rel_26/bench/verilog/
267 Full duplex control frames tested. mohor 7818d 19h /ethmac/tags/rel_26/bench/verilog/
266 Flow control test almost finished. mohor 7823d 18h /ethmac/tags/rel_26/bench/verilog/
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7824d 09h /ethmac/tags/rel_26/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7824d 21h /ethmac/tags/rel_26/bench/verilog/
254 Temp version. mohor 7826d 15h /ethmac/tags/rel_26/bench/verilog/
252 Just some updates. tadejm 7826d 18h /ethmac/tags/rel_26/bench/verilog/
243 Late collision is not reported any more. tadejm 7831d 22h /ethmac/tags/rel_26/bench/verilog/
227 Changed BIST scan signals. tadejm 7858d 18h /ethmac/tags/rel_26/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7858d 21h /ethmac/tags/rel_26/bench/verilog/

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