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[/] [ethmac/] [tags/] [rel_26/] [rtl/] - Rev 285


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Rev Log message Author Age Path
285 Binary operator used instead of unary (xnor). mohor 7173d 00h /ethmac/tags/rel_26/rtl
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 7201d 01h /ethmac/tags/rel_26/rtl
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.
mohor 7228d 19h /ethmac/tags/rel_26/rtl
280 Reset has priority in some flipflops. mohor 7306d 21h /ethmac/tags/rel_26/rtl
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.
mohor 7306d 22h /ethmac/tags/rel_26/rtl
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 7306d 22h /ethmac/tags/rel_26/rtl
276 Defer indication changed. tadejm 7306d 22h /ethmac/tags/rel_26/rtl
275 Fix MTxErr or prevent sending too big frames. mohor 7314d 02h /ethmac/tags/rel_26/rtl
272 When control packets were received, they were ignored in some cases. tadejm 7314d 22h /ethmac/tags/rel_26/rtl
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 7315d 23h /ethmac/tags/rel_26/rtl
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7316d 23h /ethmac/tags/rel_26/rtl
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 7375d 22h /ethmac/tags/rel_26/rtl
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
mohor 7376d 09h /ethmac/tags/rel_26/rtl
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).
mohor 7377d 11h /ethmac/tags/rel_26/rtl
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
mohor 7377d 11h /ethmac/tags/rel_26/rtl
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.
mohor 7377d 11h /ethmac/tags/rel_26/rtl
255 TPauseRq synchronized to tx_clk. mohor 7377d 11h /ethmac/tags/rel_26/rtl
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7378d 17h /ethmac/tags/rel_26/rtl
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 7378d 18h /ethmac/tags/rel_26/rtl
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7378d 18h /ethmac/tags/rel_26/rtl
248 wb_rst_i is used for MIIM reset. mohor 7379d 18h /ethmac/tags/rel_26/rtl
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7382d 21h /ethmac/tags/rel_26/rtl
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7383d 17h /ethmac/tags/rel_26/rtl
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7384d 13h /ethmac/tags/rel_26/rtl
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7384d 13h /ethmac/tags/rel_26/rtl
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7384d 13h /ethmac/tags/rel_26/rtl
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7384d 13h /ethmac/tags/rel_26/rtl
238 Defines fixed to use generic RAM by default. mohor 7396d 17h /ethmac/tags/rel_26/rtl
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7398d 23h /ethmac/tags/rel_26/rtl
232 fpga define added. mohor 7404d 17h /ethmac/tags/rel_26/rtl

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