URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_26/] [rtl/] - Rev 301

Rev	Log message	Author	Age	Path
255	TPauseRq synchronized to tx_clk.	mohor	7819d 11h	/ethmac/tags/rel_26/rtl/
253	r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.	mohor	7820d 17h	/ethmac/tags/rel_26/rtl/
251	When control frame (PAUSE) was sent, status was written in the eth_wishbone module and both TXB and TXC interrupts were set. Fixed. Only TXC interrupt is set.	mohor	7820d 17h	/ethmac/tags/rel_26/rtl/
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7820d 17h	/ethmac/tags/rel_26/rtl/
248	wb_rst_i is used for MIIM reset.	mohor	7821d 17h	/ethmac/tags/rel_26/rtl/
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	7824d 20h	/ethmac/tags/rel_26/rtl/
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7825d 16h	/ethmac/tags/rel_26/rtl/
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7826d 12h	/ethmac/tags/rel_26/rtl/
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	7826d 12h	/ethmac/tags/rel_26/rtl/
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7826d 13h	/ethmac/tags/rel_26/rtl/