Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_26/] [rtl/] - Rev 312


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 6877d 05h /ethmac/tags/rel_26/rtl/
306 Lapsus fixed (!we -> ~we). simons 6878d 03h /ethmac/tags/rel_26/rtl/
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 6899d 23h /ethmac/tags/rel_26/rtl/
302 mbist signals updated according to newest convention markom 6926d 10h /ethmac/tags/rel_26/rtl/
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 6937d 02h /ethmac/tags/rel_26/rtl/
297 Artisan ram instance added. simons 6990d 01h /ethmac/tags/rel_26/rtl/
288 This file was not part of the RTL before, but it should be here. simons 7026d 03h /ethmac/tags/rel_26/rtl/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 7052d 06h /ethmac/tags/rel_26/rtl/
285 Binary operator used instead of unary (xnor). mohor 7052d 06h /ethmac/tags/rel_26/rtl/
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 7080d 08h /ethmac/tags/rel_26/rtl/
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.
mohor 7108d 01h /ethmac/tags/rel_26/rtl/
280 Reset has priority in some flipflops. mohor 7186d 03h /ethmac/tags/rel_26/rtl/
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.
mohor 7186d 04h /ethmac/tags/rel_26/rtl/
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 7186d 04h /ethmac/tags/rel_26/rtl/
276 Defer indication changed. tadejm 7186d 04h /ethmac/tags/rel_26/rtl/
275 Fix MTxErr or prevent sending too big frames. mohor 7193d 08h /ethmac/tags/rel_26/rtl/
272 When control packets were received, they were ignored in some cases. tadejm 7194d 04h /ethmac/tags/rel_26/rtl/
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 7195d 06h /ethmac/tags/rel_26/rtl/
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7196d 06h /ethmac/tags/rel_26/rtl/
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 7255d 04h /ethmac/tags/rel_26/rtl/
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
mohor 7255d 16h /ethmac/tags/rel_26/rtl/
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).
mohor 7256d 17h /ethmac/tags/rel_26/rtl/
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
mohor 7256d 17h /ethmac/tags/rel_26/rtl/
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.
mohor 7256d 17h /ethmac/tags/rel_26/rtl/
255 TPauseRq synchronized to tx_clk. mohor 7256d 18h /ethmac/tags/rel_26/rtl/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7257d 23h /ethmac/tags/rel_26/rtl/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 7258d 00h /ethmac/tags/rel_26/rtl/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7258d 00h /ethmac/tags/rel_26/rtl/
248 wb_rst_i is used for MIIM reset. mohor 7259d 00h /ethmac/tags/rel_26/rtl/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7262d 03h /ethmac/tags/rel_26/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2022, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.