OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_26/] [rtl/] - Rev 322

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
322 This commit was manufactured by cvs2svn to create tag 'rel_26'. 7296d 16h /ethmac/tags/rel_26/rtl/
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries		 igorm 7296d 16h /ethmac/tags/rel_26/rtl/
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 7296d 20h /ethmac/tags/rel_26/rtl/
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 7336d 22h /ethmac/tags/rel_26/rtl/
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7439d 19h /ethmac/tags/rel_26/rtl/
306 Lapsus fixed (!we -> ~we). simons 7440d 16h /ethmac/tags/rel_26/rtl/
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7462d 13h /ethmac/tags/rel_26/rtl/
302 mbist signals updated according to newest convention markom 7489d 00h /ethmac/tags/rel_26/rtl/
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7499d 16h /ethmac/tags/rel_26/rtl/
297 Artisan ram instance added. simons 7552d 15h /ethmac/tags/rel_26/rtl/
288 This file was not part of the RTL before, but it should be here. simons 7588d 16h /ethmac/tags/rel_26/rtl/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7614d 19h /ethmac/tags/rel_26/rtl/
285 Binary operator used instead of unary (xnor). mohor 7614d 20h /ethmac/tags/rel_26/rtl/
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 7642d 21h /ethmac/tags/rel_26/rtl/
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.		 mohor 7670d 15h /ethmac/tags/rel_26/rtl/
280 Reset has priority in some flipflops. mohor 7748d 16h /ethmac/tags/rel_26/rtl/
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.		 mohor 7748d 18h /ethmac/tags/rel_26/rtl/
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 7748d 18h /ethmac/tags/rel_26/rtl/
276 Defer indication changed. tadejm 7748d 18h /ethmac/tags/rel_26/rtl/
275 Fix MTxErr or prevent sending too big frames. mohor 7755d 22h /ethmac/tags/rel_26/rtl/
272 When control packets were received, they were ignored in some cases. tadejm 7756d 17h /ethmac/tags/rel_26/rtl/
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7757d 19h /ethmac/tags/rel_26/rtl/
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7758d 19h /ethmac/tags/rel_26/rtl/
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7817d 18h /ethmac/tags/rel_26/rtl/
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7818d 05h /ethmac/tags/rel_26/rtl/
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7819d 07h /ethmac/tags/rel_26/rtl/
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7819d 07h /ethmac/tags/rel_26/rtl/
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7819d 07h /ethmac/tags/rel_26/rtl/
255 TPauseRq synchronized to tx_clk. mohor 7819d 07h /ethmac/tags/rel_26/rtl/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7820d 13h /ethmac/tags/rel_26/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.