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[/] [ethmac/] [tags/] [rel_26/] [rtl/] [verilog/] - Rev 338

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Rev Log message Author Age Path
338 root 3817d 17h /ethmac/tags/rel_26/rtl/verilog/
335 New directory structure. root 3874d 22h /ethmac/tags/rel_26/rtl/verilog/
322 This commit was manufactured by cvs2svn to create tag 'rel_26'. 5652d 17h /ethmac/tags/rel_26/rtl/verilog/
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 5652d 17h /ethmac/tags/rel_26/rtl/verilog/
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 5652d 20h /ethmac/tags/rel_26/rtl/verilog/
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 5692d 22h /ethmac/tags/rel_26/rtl/verilog/
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 5795d 19h /ethmac/tags/rel_26/rtl/verilog/
306 Lapsus fixed (!we -> ~we). simons 5796d 17h /ethmac/tags/rel_26/rtl/verilog/
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 5818d 14h /ethmac/tags/rel_26/rtl/verilog/
302 mbist signals updated according to newest convention markom 5845d 00h /ethmac/tags/rel_26/rtl/verilog/
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 5855d 16h /ethmac/tags/rel_26/rtl/verilog/
297 Artisan ram instance added. simons 5908d 15h /ethmac/tags/rel_26/rtl/verilog/
288 This file was not part of the RTL before, but it should be here. simons 5944d 17h /ethmac/tags/rel_26/rtl/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 5970d 20h /ethmac/tags/rel_26/rtl/verilog/
285 Binary operator used instead of unary (xnor). mohor 5970d 21h /ethmac/tags/rel_26/rtl/verilog/
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 5998d 22h /ethmac/tags/rel_26/rtl/verilog/
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.
mohor 6026d 16h /ethmac/tags/rel_26/rtl/verilog/
280 Reset has priority in some flipflops. mohor 6104d 17h /ethmac/tags/rel_26/rtl/verilog/
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.
mohor 6104d 18h /ethmac/tags/rel_26/rtl/verilog/
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 6104d 18h /ethmac/tags/rel_26/rtl/verilog/

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