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[/] [ethmac/] [tags/] [rel_26/] [rtl/] [verilog/] - Rev 358

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Rev	Log message	Author	Age	Path
338		root	5468d 13h	/ethmac/tags/rel_26/rtl/verilog/
335	New directory structure.	root	5525d 18h	/ethmac/tags/rel_26/rtl/verilog/
322	This commit was manufactured by cvs2svn to create tag 'rel_26'.		7303d 13h	/ethmac/tags/rel_26/rtl/verilog/
321	- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the previous update of the core. - TxBDAddress is set to 0 after the TX is enabled in the MODER register. - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER register. (thanks to Mathias and Torbjorn) - Multicast reception was fixed. Thanks to Ulrich Gries	igorm	7303d 13h	/ethmac/tags/rel_26/rtl/verilog/
320	TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.	igorm	7303d 17h	/ethmac/tags/rel_26/rtl/verilog/
317	Multicast detection fixed. Only the LSB of the first byte is checked.	igorm	7343d 19h	/ethmac/tags/rel_26/rtl/verilog/
312	Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.	tadejm	7446d 16h	/ethmac/tags/rel_26/rtl/verilog/
306	Lapsus fixed (!we -> ~we).	simons	7447d 13h	/ethmac/tags/rel_26/rtl/verilog/
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7469d 10h	/ethmac/tags/rel_26/rtl/verilog/
302	mbist signals updated according to newest convention	markom	7495d 21h	/ethmac/tags/rel_26/rtl/verilog/
301	Update RxEnSync only when mrxdv_pad_i is inactive (LOW).	knguyen	7506d 13h	/ethmac/tags/rel_26/rtl/verilog/
297	Artisan ram instance added.	simons	7559d 12h	/ethmac/tags/rel_26/rtl/verilog/
288	This file was not part of the RTL before, but it should be here.	simons	7595d 13h	/ethmac/tags/rel_26/rtl/verilog/
286	Define file in eth_cop.v is changed to eth_defines.v. Some defines were moved from tb_eth_defines.v to eth_defines.v.	mohor	7621d 16h	/ethmac/tags/rel_26/rtl/verilog/
285	Binary operator used instead of unary (xnor).	mohor	7621d 17h	/ethmac/tags/rel_26/rtl/verilog/
284	Busy was set 2 cycles too late. Reported by Dennis Scott.	mohor	7649d 18h	/ethmac/tags/rel_26/rtl/verilog/
283	RxBDAddress was updated also when value to r_TxBDNum was written with greater value than allowed.	mohor	7677d 12h	/ethmac/tags/rel_26/rtl/verilog/
280	Reset has priority in some flipflops.	mohor	7755d 13h	/ethmac/tags/rel_26/rtl/verilog/
278	A new bug (entered with previous update) fixed. When abort occured sometimes data transmission was blocked.	mohor	7755d 15h	/ethmac/tags/rel_26/rtl/verilog/
277	When padding was enabled and crc disabled, frame was not ended correctly.	mohor	7755d 15h	/ethmac/tags/rel_26/rtl/verilog/

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[/] [ethmac/] [tags/] [rel_26/] [rtl/] [verilog/] - Rev 358

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