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[/] [ethmac/] [tags/] [rel_26/] [rtl] - Rev 259

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Rev Log message Author Age Path
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7836d 10h /ethmac/tags/rel_26/rtl
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7839d 10h /ethmac/tags/rel_26/rtl
218 Typo error fixed. (When using Bist) mohor 7839d 12h /ethmac/tags/rel_26/rtl
214 Signals for WISHBONE B3 compliant interface added. mohor 7840d 09h /ethmac/tags/rel_26/rtl
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7840d 09h /ethmac/tags/rel_26/rtl
212 Minor $display change. mohor 7840d 09h /ethmac/tags/rel_26/rtl
211 Bist added. mohor 7840d 09h /ethmac/tags/rel_26/rtl
210 BIST added. mohor 7840d 09h /ethmac/tags/rel_26/rtl
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7857d 07h /ethmac/tags/rel_26/rtl
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 7857d 07h /ethmac/tags/rel_26/rtl

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