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Rev Log message Author Age Path
216 Bist signals added. mohor 6591d 08h /ethmac/tags/rel_27/
215 Bist supported. mohor 6591d 09h /ethmac/tags/rel_27/
214 Signals for WISHBONE B3 compliant interface added. mohor 6592d 04h /ethmac/tags/rel_27/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6592d 04h /ethmac/tags/rel_27/
212 Minor $display change. mohor 6592d 05h /ethmac/tags/rel_27/
211 Bist added. mohor 6592d 05h /ethmac/tags/rel_27/
210 BIST added. mohor 6592d 05h /ethmac/tags/rel_27/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6593d 08h /ethmac/tags/rel_27/
208 Virtual Silicon RAMs moved to lib directory tadej 6609d 02h /ethmac/tags/rel_27/
207 Virtual Silicon RAM support fixed tadej 6609d 02h /ethmac/tags/rel_27/
206 Virtual Silicon RAM added to the simulation. mohor 6609d 02h /ethmac/tags/rel_27/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 6609d 03h /ethmac/tags/rel_27/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6609d 03h /ethmac/tags/rel_27/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
mohor 6609d 03h /ethmac/tags/rel_27/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 6612d 04h /ethmac/tags/rel_27/
201 Core size added to the document. mohor 6612d 05h /ethmac/tags/rel_27/
200 File with lower case checked in instead. mohor 6612d 05h /ethmac/tags/rel_27/
199 Datasheet name changed to lower case name. mohor 6612d 05h /ethmac/tags/rel_27/
198 Removed file. File with name in lower case will be added instead. mohor 6612d 05h /ethmac/tags/rel_27/
197 Ethernet Data Sheet. mohor 6612d 05h /ethmac/tags/rel_27/

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