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[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog/] - Rev 188

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Rev Log message Author Age Path
188 PHY changed. tadej 7885d 19h /ethmac/tags/rel_27/bench/verilog/
182 Full duplex test improved. tadej 7886d 21h /ethmac/tags/rel_27/bench/verilog/
181 MIIM test look better. mohor 7887d 00h /ethmac/tags/rel_27/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 7889d 20h /ethmac/tags/rel_27/bench/verilog/
179 Beautiful tests merget together mohor 7889d 20h /ethmac/tags/rel_27/bench/verilog/
178 Rearanged testcases mohor 7889d 20h /ethmac/tags/rel_27/bench/verilog/
177 Bug in MIIM fixed. mohor 7890d 00h /ethmac/tags/rel_27/bench/verilog/
170 Headers changed. mohor 7890d 03h /ethmac/tags/rel_27/bench/verilog/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7890d 03h /ethmac/tags/rel_27/bench/verilog/
158 Typo fixed. mohor 7894d 23h /ethmac/tags/rel_27/bench/verilog/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7897d 04h /ethmac/tags/rel_27/bench/verilog/
156 Valid testbench. mohor 7897d 04h /ethmac/tags/rel_27/bench/verilog/
155 Minor changes. mohor 7897d 04h /ethmac/tags/rel_27/bench/verilog/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7939d 22h /ethmac/tags/rel_27/bench/verilog/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7941d 22h /ethmac/tags/rel_27/bench/verilog/
117 Clock mrx_clk set to 2.5 MHz. mohor 7946d 01h /ethmac/tags/rel_27/bench/verilog/
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 7946d 01h /ethmac/tags/rel_27/bench/verilog/
108 Testbench supports unaligned accesses. mohor 8023d 05h /ethmac/tags/rel_27/bench/verilog/
107 TX_BUF_BASE changed. mohor 8023d 05h /ethmac/tags/rel_27/bench/verilog/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8068d 02h /ethmac/tags/rel_27/bench/verilog/

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