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Rev Log message Author Age Path
188 PHY changed. tadej 6582d 08h /ethmac/tags/rel_27/bench/verilog/
182 Full duplex test improved. tadej 6583d 10h /ethmac/tags/rel_27/bench/verilog/
181 MIIM test look better. mohor 6583d 13h /ethmac/tags/rel_27/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 6586d 09h /ethmac/tags/rel_27/bench/verilog/
179 Beautiful tests merget together mohor 6586d 09h /ethmac/tags/rel_27/bench/verilog/
178 Rearanged testcases mohor 6586d 09h /ethmac/tags/rel_27/bench/verilog/
177 Bug in MIIM fixed. mohor 6586d 13h /ethmac/tags/rel_27/bench/verilog/
170 Headers changed. mohor 6586d 16h /ethmac/tags/rel_27/bench/verilog/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 6586d 16h /ethmac/tags/rel_27/bench/verilog/
158 Typo fixed. mohor 6591d 12h /ethmac/tags/rel_27/bench/verilog/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 6593d 17h /ethmac/tags/rel_27/bench/verilog/
156 Valid testbench. mohor 6593d 17h /ethmac/tags/rel_27/bench/verilog/
155 Minor changes. mohor 6593d 17h /ethmac/tags/rel_27/bench/verilog/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 6636d 11h /ethmac/tags/rel_27/bench/verilog/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 6638d 11h /ethmac/tags/rel_27/bench/verilog/
117 Clock mrx_clk set to 2.5 MHz. mohor 6642d 14h /ethmac/tags/rel_27/bench/verilog/
116 Testing environment also includes traffic cop, memory interface and host
mohor 6642d 14h /ethmac/tags/rel_27/bench/verilog/
108 Testbench supports unaligned accesses. mohor 6719d 18h /ethmac/tags/rel_27/bench/verilog/
107 TX_BUF_BASE changed. mohor 6719d 18h /ethmac/tags/rel_27/bench/verilog/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
mohor 6764d 15h /ethmac/tags/rel_27/bench/verilog/

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