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[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog/] - Rev 209

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Rev Log message Author Age Path
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6631d 19h /ethmac/tags/rel_27/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 6650d 18h /ethmac/tags/rel_27/bench/verilog/
192 Some additional reports added tadej 6652d 15h /ethmac/tags/rel_27/bench/verilog/
191 Bug repaired in eth_phy device tadej 6652d 15h /ethmac/tags/rel_27/bench/verilog/
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).
mohor 6652d 16h /ethmac/tags/rel_27/bench/verilog/
188 PHY changed. tadej 6653d 12h /ethmac/tags/rel_27/bench/verilog/
182 Full duplex test improved. tadej 6654d 15h /ethmac/tags/rel_27/bench/verilog/
181 MIIM test look better. mohor 6654d 17h /ethmac/tags/rel_27/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 6657d 13h /ethmac/tags/rel_27/bench/verilog/
179 Beautiful tests merget together mohor 6657d 14h /ethmac/tags/rel_27/bench/verilog/
178 Rearanged testcases mohor 6657d 14h /ethmac/tags/rel_27/bench/verilog/
177 Bug in MIIM fixed. mohor 6657d 18h /ethmac/tags/rel_27/bench/verilog/
170 Headers changed. mohor 6657d 20h /ethmac/tags/rel_27/bench/verilog/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 6657d 21h /ethmac/tags/rel_27/bench/verilog/
158 Typo fixed. mohor 6662d 16h /ethmac/tags/rel_27/bench/verilog/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 6664d 21h /ethmac/tags/rel_27/bench/verilog/
156 Valid testbench. mohor 6664d 21h /ethmac/tags/rel_27/bench/verilog/
155 Minor changes. mohor 6664d 22h /ethmac/tags/rel_27/bench/verilog/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 6707d 15h /ethmac/tags/rel_27/bench/verilog/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 6709d 16h /ethmac/tags/rel_27/bench/verilog/

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