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[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog/] - Rev 216

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Rev Log message Author Age Path
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 6668d 07h /ethmac/tags/rel_27/bench/verilog/
117 Clock mrx_clk set to 2.5 MHz. mohor 6672d 10h /ethmac/tags/rel_27/bench/verilog/
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 6672d 10h /ethmac/tags/rel_27/bench/verilog/
108 Testbench supports unaligned accesses. mohor 6749d 13h /ethmac/tags/rel_27/bench/verilog/
107 TX_BUF_BASE changed. mohor 6749d 13h /ethmac/tags/rel_27/bench/verilog/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 6794d 11h /ethmac/tags/rel_27/bench/verilog/
80 Small fixes for external/internal DMA missmatches. mohor 6815d 07h /ethmac/tags/rel_27/bench/verilog/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 6825d 11h /ethmac/tags/rel_27/bench/verilog/
66 Testbench fixed, code simplified, unused signals removed. mohor 6825d 16h /ethmac/tags/rel_27/bench/verilog/
51 Added separate tests for Multicast, Unicast, Broadcast billditt 6827d 04h /ethmac/tags/rel_27/bench/verilog/

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