URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog/] - Rev 216

Rev	Log message	Author	Age	Path
121	gsr added for use when ETH_XILINX_RAMB4 define is set.	mohor	7940d 20h	/ethmac/tags/rel_27/bench/verilog/
117	Clock mrx_clk set to 2.5 MHz.	mohor	7944d 22h	/ethmac/tags/rel_27/bench/verilog/
116	Testing environment also includes traffic cop, memory interface and host interface.	mohor	7944d 22h	/ethmac/tags/rel_27/bench/verilog/
108	Testbench supports unaligned accesses.	mohor	8022d 02h	/ethmac/tags/rel_27/bench/verilog/
107	TX_BUF_BASE changed.	mohor	8022d 02h	/ethmac/tags/rel_27/bench/verilog/
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8066d 23h	/ethmac/tags/rel_27/bench/verilog/
80	Small fixes for external/internal DMA missmatches.	mohor	8087d 19h	/ethmac/tags/rel_27/bench/verilog/
67	EXTERNAL_DMA used instead of WISHBONE_DMA.	mohor	8097d 23h	/ethmac/tags/rel_27/bench/verilog/
66	Testbench fixed, code simplified, unused signals removed.	mohor	8098d 05h	/ethmac/tags/rel_27/bench/verilog/
51	Added separate tests for Multicast, Unicast, Broadcast	billditt	8099d 16h	/ethmac/tags/rel_27/bench/verilog/