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[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog/] - Rev 254

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Rev Log message Author Age Path
254 Temp version. mohor 7799d 20h /ethmac/tags/rel_27/bench/verilog/
252 Just some updates. tadejm 7799d 23h /ethmac/tags/rel_27/bench/verilog/
243 Late collision is not reported any more. tadejm 7805d 03h /ethmac/tags/rel_27/bench/verilog/
227 Changed BIST scan signals. tadejm 7831d 23h /ethmac/tags/rel_27/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7832d 02h /ethmac/tags/rel_27/bench/verilog/
216 Bist signals added. mohor 7839d 03h /ethmac/tags/rel_27/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7841d 03h /ethmac/tags/rel_27/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 7860d 02h /ethmac/tags/rel_27/bench/verilog/
192 Some additional reports added tadej 7861d 23h /ethmac/tags/rel_27/bench/verilog/
191 Bug repaired in eth_phy device tadej 7861d 23h /ethmac/tags/rel_27/bench/verilog/
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).
mohor 7862d 00h /ethmac/tags/rel_27/bench/verilog/
188 PHY changed. tadej 7862d 20h /ethmac/tags/rel_27/bench/verilog/
182 Full duplex test improved. tadej 7863d 23h /ethmac/tags/rel_27/bench/verilog/
181 MIIM test look better. mohor 7864d 01h /ethmac/tags/rel_27/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 7866d 21h /ethmac/tags/rel_27/bench/verilog/
179 Beautiful tests merget together mohor 7866d 22h /ethmac/tags/rel_27/bench/verilog/
178 Rearanged testcases mohor 7866d 22h /ethmac/tags/rel_27/bench/verilog/
177 Bug in MIIM fixed. mohor 7867d 02h /ethmac/tags/rel_27/bench/verilog/
170 Headers changed. mohor 7867d 04h /ethmac/tags/rel_27/bench/verilog/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7867d 04h /ethmac/tags/rel_27/bench/verilog/

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