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[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog/] - Rev 274

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Rev Log message Author Age Path
274 Backup version. Not fully working. tadejm 7756d 17h /ethmac/tags/rel_27/bench/verilog/
267 Full duplex control frames tested. mohor 7812d 21h /ethmac/tags/rel_27/bench/verilog/
266 Flow control test almost finished. mohor 7817d 19h /ethmac/tags/rel_27/bench/verilog/
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7818d 11h /ethmac/tags/rel_27/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7818d 23h /ethmac/tags/rel_27/bench/verilog/
254 Temp version. mohor 7820d 16h /ethmac/tags/rel_27/bench/verilog/
252 Just some updates. tadejm 7820d 19h /ethmac/tags/rel_27/bench/verilog/
243 Late collision is not reported any more. tadejm 7826d 00h /ethmac/tags/rel_27/bench/verilog/
227 Changed BIST scan signals. tadejm 7852d 20h /ethmac/tags/rel_27/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7852d 23h /ethmac/tags/rel_27/bench/verilog/
216 Bist signals added. mohor 7859d 23h /ethmac/tags/rel_27/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7862d 00h /ethmac/tags/rel_27/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 7880d 22h /ethmac/tags/rel_27/bench/verilog/
192 Some additional reports added tadej 7882d 19h /ethmac/tags/rel_27/bench/verilog/
191 Bug repaired in eth_phy device tadej 7882d 19h /ethmac/tags/rel_27/bench/verilog/
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).		 mohor 7882d 20h /ethmac/tags/rel_27/bench/verilog/
188 PHY changed. tadej 7883d 17h /ethmac/tags/rel_27/bench/verilog/
182 Full duplex test improved. tadej 7884d 19h /ethmac/tags/rel_27/bench/verilog/
181 MIIM test look better. mohor 7884d 22h /ethmac/tags/rel_27/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 7887d 18h /ethmac/tags/rel_27/bench/verilog/
179 Beautiful tests merget together mohor 7887d 18h /ethmac/tags/rel_27/bench/verilog/
178 Rearanged testcases mohor 7887d 18h /ethmac/tags/rel_27/bench/verilog/
177 Bug in MIIM fixed. mohor 7887d 22h /ethmac/tags/rel_27/bench/verilog/
170 Headers changed. mohor 7888d 00h /ethmac/tags/rel_27/bench/verilog/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7888d 01h /ethmac/tags/rel_27/bench/verilog/
158 Typo fixed. mohor 7892d 21h /ethmac/tags/rel_27/bench/verilog/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7895d 02h /ethmac/tags/rel_27/bench/verilog/
156 Valid testbench. mohor 7895d 02h /ethmac/tags/rel_27/bench/verilog/
155 Minor changes. mohor 7895d 02h /ethmac/tags/rel_27/bench/verilog/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7937d 20h /ethmac/tags/rel_27/bench/verilog/

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