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[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog/] - Rev 338

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Rev Log message Author Age Path
338 root 3847d 08h /ethmac/tags/rel_27/bench/verilog/
335 New directory structure. root 3904d 14h /ethmac/tags/rel_27/bench/verilog/
324 This commit was manufactured by cvs2svn to create tag 'rel_27'. 5678d 13h /ethmac/tags/rel_27/bench/verilog/
318 Latest Ethernet IP core testbench. tadejm 5713d 08h /ethmac/tags/rel_27/bench/verilog/
315 Updated testbench. Some more testcases, some repaired. tadejm 5825d 11h /ethmac/tags/rel_27/bench/verilog/
302 mbist signals updated according to newest convention markom 5874d 16h /ethmac/tags/rel_27/bench/verilog/
299 Artisan RAMs added. mohor 5932d 12h /ethmac/tags/rel_27/bench/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 6000d 12h /ethmac/tags/rel_27/bench/verilog/
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 6133d 08h /ethmac/tags/rel_27/bench/verilog/
279 Underrun test fixed. Many other tests fixed. mohor 6134d 10h /ethmac/tags/rel_27/bench/verilog/
274 Backup version. Not fully working. tadejm 6142d 04h /ethmac/tags/rel_27/bench/verilog/
267 Full duplex control frames tested. mohor 6198d 07h /ethmac/tags/rel_27/bench/verilog/
266 Flow control test almost finished. mohor 6203d 06h /ethmac/tags/rel_27/bench/verilog/
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 6203d 22h /ethmac/tags/rel_27/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 6204d 10h /ethmac/tags/rel_27/bench/verilog/
254 Temp version. mohor 6206d 03h /ethmac/tags/rel_27/bench/verilog/
252 Just some updates. tadejm 6206d 06h /ethmac/tags/rel_27/bench/verilog/
243 Late collision is not reported any more. tadejm 6211d 11h /ethmac/tags/rel_27/bench/verilog/
227 Changed BIST scan signals. tadejm 6238d 07h /ethmac/tags/rel_27/bench/verilog/
223 Some code changed due to bug fixes. tadejm 6238d 10h /ethmac/tags/rel_27/bench/verilog/
216 Bist signals added. mohor 6245d 10h /ethmac/tags/rel_27/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6247d 10h /ethmac/tags/rel_27/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 6266d 09h /ethmac/tags/rel_27/bench/verilog/
192 Some additional reports added tadej 6268d 06h /ethmac/tags/rel_27/bench/verilog/
191 Bug repaired in eth_phy device tadej 6268d 06h /ethmac/tags/rel_27/bench/verilog/
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).
mohor 6268d 07h /ethmac/tags/rel_27/bench/verilog/
188 PHY changed. tadej 6269d 04h /ethmac/tags/rel_27/bench/verilog/
182 Full duplex test improved. tadej 6270d 06h /ethmac/tags/rel_27/bench/verilog/
181 MIIM test look better. mohor 6270d 09h /ethmac/tags/rel_27/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 6273d 04h /ethmac/tags/rel_27/bench/verilog/

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