OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_27/] [rtl/] [verilog/] - Rev 338

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
338 root 3984d 05h /ethmac/tags/rel_27/rtl/verilog/
335 New directory structure. root 4041d 10h /ethmac/tags/rel_27/rtl/verilog/
324 This commit was manufactured by cvs2svn to create tag 'rel_27'. 5815d 09h /ethmac/tags/rel_27/rtl/verilog/
323 Accidently deleted line put back. igorm 5815d 09h /ethmac/tags/rel_27/rtl/verilog/
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 5819d 04h /ethmac/tags/rel_27/rtl/verilog/
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 5819d 08h /ethmac/tags/rel_27/rtl/verilog/
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 5859d 10h /ethmac/tags/rel_27/rtl/verilog/
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 5962d 07h /ethmac/tags/rel_27/rtl/verilog/
306 Lapsus fixed (!we -> ~we). simons 5963d 05h /ethmac/tags/rel_27/rtl/verilog/
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 5985d 01h /ethmac/tags/rel_27/rtl/verilog/
302 mbist signals updated according to newest convention markom 6011d 12h /ethmac/tags/rel_27/rtl/verilog/
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 6022d 04h /ethmac/tags/rel_27/rtl/verilog/
297 Artisan ram instance added. simons 6075d 03h /ethmac/tags/rel_27/rtl/verilog/
288 This file was not part of the RTL before, but it should be here. simons 6111d 05h /ethmac/tags/rel_27/rtl/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 6137d 08h /ethmac/tags/rel_27/rtl/verilog/
285 Binary operator used instead of unary (xnor). mohor 6137d 08h /ethmac/tags/rel_27/rtl/verilog/
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 6165d 10h /ethmac/tags/rel_27/rtl/verilog/
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.
mohor 6193d 03h /ethmac/tags/rel_27/rtl/verilog/
280 Reset has priority in some flipflops. mohor 6271d 05h /ethmac/tags/rel_27/rtl/verilog/
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.
mohor 6271d 06h /ethmac/tags/rel_27/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.