URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_27/] [rtl/] [verilog/] [eth_spram_256x32.v] - Rev 338

Rev	Log message	Author	Age	Path
338		root	5459d 17h	/ethmac/tags/rel_27/rtl/verilog/eth_spram_256x32.v
335	New directory structure.	root	5516d 23h	/ethmac/tags/rel_27/rtl/verilog/eth_spram_256x32.v
324	This commit was manufactured by cvs2svn to create tag 'rel_27'.		7290d 22h	/ethmac/tags/rel_27/rtl/verilog/eth_spram_256x32.v
312	Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.	tadejm	7437d 20h	/ethmac/tags/rel_27/rtl/verilog/eth_spram_256x32.v
306	Lapsus fixed (!we -> ~we).	simons	7438d 18h	/ethmac/tags/rel_27/rtl/verilog/eth_spram_256x32.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7460d 14h	/ethmac/tags/rel_27/rtl/verilog/eth_spram_256x32.v
302	mbist signals updated according to newest convention	markom	7487d 01h	/ethmac/tags/rel_27/rtl/verilog/eth_spram_256x32.v
297	Artisan ram instance added.	simons	7550d 16h	/ethmac/tags/rel_27/rtl/verilog/eth_spram_256x32.v
227	Changed BIST scan signals.	tadejm	7850d 16h	/ethmac/tags/rel_27/rtl/verilog/eth_spram_256x32.v
210	BIST added.	mohor	7858d 16h	/ethmac/tags/rel_27/rtl/verilog/eth_spram_256x32.v
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7875d 14h	/ethmac/tags/rel_27/rtl/verilog/eth_spram_256x32.v
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	7937d 16h	/ethmac/tags/rel_27/rtl/verilog/eth_spram_256x32.v