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116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 7945d 01h /ethmac/tags/rel_3/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7945d 23h /ethmac/tags/rel_3/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7946d 20h /ethmac/tags/rel_3/
113 RxPointer bug fixed. mohor 7953d 12h /ethmac/tags/rel_3/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7954d 02h /ethmac/tags/rel_3/
111 Master state machine had a bug when switching from master write to
master read.
mohor 7954d 15h /ethmac/tags/rel_3/
110 m_wb_cyc_o signal released after every single transfer. mohor 7954d 18h /ethmac/tags/rel_3/
109 Comment removed. mohor 7954d 19h /ethmac/tags/rel_3/
108 Testbench supports unaligned accesses. mohor 8022d 05h /ethmac/tags/rel_3/
107 TX_BUF_BASE changed. mohor 8022d 05h /ethmac/tags/rel_3/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8022d 05h /ethmac/tags/rel_3/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 8031d 06h /ethmac/tags/rel_3/
104 FCS should not be included in NibbleMinFl. mohor 8033d 00h /ethmac/tags/rel_3/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 8033d 01h /ethmac/tags/rel_3/
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 8033d 01h /ethmac/tags/rel_3/
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8033d 01h /ethmac/tags/rel_3/
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 8033d 01h /ethmac/tags/rel_3/
99 Document revised. mohor 8040d 00h /ethmac/tags/rel_3/
98 Document revised. mohor 8040d 01h /ethmac/tags/rel_3/
97 Small typo fixed. lampret 8056d 23h /ethmac/tags/rel_3/

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