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[/] [ethmac/] [tags/] [rel_3/] - Rev 122

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Rev Log message Author Age Path
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 6424d 08h /ethmac/tags/rel_3/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 6424d 08h /ethmac/tags/rel_3/
120 Unused files removed. mohor 6424d 09h /ethmac/tags/rel_3/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 6424d 09h /ethmac/tags/rel_3/
118 ShiftEnded synchronization changed. mohor 6428d 00h /ethmac/tags/rel_3/
117 Clock mrx_clk set to 2.5 MHz. mohor 6428d 11h /ethmac/tags/rel_3/
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 6428d 11h /ethmac/tags/rel_3/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 6429d 08h /ethmac/tags/rel_3/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 6430d 06h /ethmac/tags/rel_3/
113 RxPointer bug fixed. mohor 6436d 22h /ethmac/tags/rel_3/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 6437d 11h /ethmac/tags/rel_3/
111 Master state machine had a bug when switching from master write to
master read.
mohor 6438d 01h /ethmac/tags/rel_3/
110 m_wb_cyc_o signal released after every single transfer. mohor 6438d 04h /ethmac/tags/rel_3/
109 Comment removed. mohor 6438d 04h /ethmac/tags/rel_3/
108 Testbench supports unaligned accesses. mohor 6505d 14h /ethmac/tags/rel_3/
107 TX_BUF_BASE changed. mohor 6505d 14h /ethmac/tags/rel_3/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 6505d 14h /ethmac/tags/rel_3/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 6514d 16h /ethmac/tags/rel_3/
104 FCS should not be included in NibbleMinFl. mohor 6516d 10h /ethmac/tags/rel_3/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 6516d 10h /ethmac/tags/rel_3/

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