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[/] [ethmac/] [tags/] [rel_3/] - Rev 122

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Rev	Log message	Author	Age	Path
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	7939d 13h	/ethmac/tags/rel_3/
121	gsr added for use when ETH_XILINX_RAMB4 define is set.	mohor	7939d 13h	/ethmac/tags/rel_3/
120	Unused files removed.	mohor	7939d 14h	/ethmac/tags/rel_3/
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7939d 14h	/ethmac/tags/rel_3/
118	ShiftEnded synchronization changed.	mohor	7943d 05h	/ethmac/tags/rel_3/
117	Clock mrx_clk set to 2.5 MHz.	mohor	7943d 15h	/ethmac/tags/rel_3/
116	Testing environment also includes traffic cop, memory interface and host interface.	mohor	7943d 15h	/ethmac/tags/rel_3/
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7944d 13h	/ethmac/tags/rel_3/
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	7945d 10h	/ethmac/tags/rel_3/
113	RxPointer bug fixed.	mohor	7952d 02h	/ethmac/tags/rel_3/
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7952d 16h	/ethmac/tags/rel_3/
111	Master state machine had a bug when switching from master write to master read.	mohor	7953d 05h	/ethmac/tags/rel_3/
110	m_wb_cyc_o signal released after every single transfer.	mohor	7953d 09h	/ethmac/tags/rel_3/
109	Comment removed.	mohor	7953d 09h	/ethmac/tags/rel_3/
108	Testbench supports unaligned accesses.	mohor	8020d 19h	/ethmac/tags/rel_3/
107	TX_BUF_BASE changed.	mohor	8020d 19h	/ethmac/tags/rel_3/
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8020d 19h	/ethmac/tags/rel_3/
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8029d 20h	/ethmac/tags/rel_3/
104	FCS should not be included in NibbleMinFl.	mohor	8031d 14h	/ethmac/tags/rel_3/
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8031d 15h	/ethmac/tags/rel_3/

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Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_3/] - Rev 122

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