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[/] [ethmac/] [tags/] [rel_3/] - Rev 127


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Rev Log message Author Age Path
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 7001d 05h /ethmac/tags/rel_3
126 InvalidSymbol generation changed. mohor 7001d 05h /ethmac/tags/rel_3
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
mohor 7001d 05h /ethmac/tags/rel_3
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7001d 06h /ethmac/tags/rel_3
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7003d 07h /ethmac/tags/rel_3
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7003d 07h /ethmac/tags/rel_3
120 Unused files removed. mohor 7003d 08h /ethmac/tags/rel_3
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7003d 08h /ethmac/tags/rel_3
118 ShiftEnded synchronization changed. mohor 7006d 23h /ethmac/tags/rel_3
117 Clock mrx_clk set to 2.5 MHz. mohor 7007d 09h /ethmac/tags/rel_3
116 Testing environment also includes traffic cop, memory interface and host
mohor 7007d 09h /ethmac/tags/rel_3
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7008d 07h /ethmac/tags/rel_3
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7009d 05h /ethmac/tags/rel_3
113 RxPointer bug fixed. mohor 7015d 21h /ethmac/tags/rel_3
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7016d 10h /ethmac/tags/rel_3
111 Master state machine had a bug when switching from master write to
master read.
mohor 7017d 00h /ethmac/tags/rel_3
110 m_wb_cyc_o signal released after every single transfer. mohor 7017d 03h /ethmac/tags/rel_3
109 Comment removed. mohor 7017d 03h /ethmac/tags/rel_3
108 Testbench supports unaligned accesses. mohor 7084d 13h /ethmac/tags/rel_3
107 TX_BUF_BASE changed. mohor 7084d 13h /ethmac/tags/rel_3

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