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[/] [ethmac/] [tags/] [rel_3/] - Rev 132

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132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 6575d 22h /ethmac/tags/rel_3/
131 LinkFail signal was not latching appropriate bit. mohor 6575d 22h /ethmac/tags/rel_3/
130 First draft of the Ethernet design document. Not a finished version. Still many
things missing.
mohor 6575d 22h /ethmac/tags/rel_3/
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
interfaces:
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 6575d 23h /ethmac/tags/rel_3/
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 6595d 21h /ethmac/tags/rel_3/
126 InvalidSymbol generation changed. mohor 6595d 22h /ethmac/tags/rel_3/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 6595d 22h /ethmac/tags/rel_3/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 6595d 23h /ethmac/tags/rel_3/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 6597d 23h /ethmac/tags/rel_3/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 6597d 23h /ethmac/tags/rel_3/
120 Unused files removed. mohor 6598d 00h /ethmac/tags/rel_3/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 6598d 00h /ethmac/tags/rel_3/
118 ShiftEnded synchronization changed. mohor 6601d 15h /ethmac/tags/rel_3/
117 Clock mrx_clk set to 2.5 MHz. mohor 6602d 02h /ethmac/tags/rel_3/
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 6602d 02h /ethmac/tags/rel_3/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 6603d 00h /ethmac/tags/rel_3/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 6603d 21h /ethmac/tags/rel_3/
113 RxPointer bug fixed. mohor 6610d 13h /ethmac/tags/rel_3/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 6611d 03h /ethmac/tags/rel_3/
111 Master state machine had a bug when switching from master write to
master read.
mohor 6611d 16h /ethmac/tags/rel_3/
110 m_wb_cyc_o signal released after every single transfer. mohor 6611d 19h /ethmac/tags/rel_3/
109 Comment removed. mohor 6611d 20h /ethmac/tags/rel_3/
108 Testbench supports unaligned accesses. mohor 6679d 06h /ethmac/tags/rel_3/
107 TX_BUF_BASE changed. mohor 6679d 06h /ethmac/tags/rel_3/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 6679d 06h /ethmac/tags/rel_3/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 6688d 07h /ethmac/tags/rel_3/
104 FCS should not be included in NibbleMinFl. mohor 6690d 01h /ethmac/tags/rel_3/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 6690d 02h /ethmac/tags/rel_3/
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 6690d 02h /ethmac/tags/rel_3/
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 6690d 02h /ethmac/tags/rel_3/

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