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Rev Log message Author Age Path
338 root 3784d 14h /ethmac/tags/rel_3/
335 New directory structure. root 3841d 19h /ethmac/tags/rel_3/
142 This commit was manufactured by cvs2svn to create tag 'rel_3'. 6238d 07h /ethmac/tags/rel_3/
141 Syntax error fixed. mohor 6238d 07h /ethmac/tags/rel_3/
140 Syntax error fixed. mohor 6238d 07h /ethmac/tags/rel_3/
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 6238d 07h /ethmac/tags/rel_3/
138 Synchronous reset added. mohor 6238d 07h /ethmac/tags/rel_3/
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.
mohor 6238d 07h /ethmac/tags/rel_3/
136 Parameter ResetValue changed to capital letters. mohor 6238d 17h /ethmac/tags/rel_3/
135 New revision. External DMA removed, TX_BD_NUM changed. mohor 6240d 09h /ethmac/tags/rel_3/
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 6240d 10h /ethmac/tags/rel_3/
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).
mohor 6240d 11h /ethmac/tags/rel_3/
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 6240d 11h /ethmac/tags/rel_3/
131 LinkFail signal was not latching appropriate bit. mohor 6240d 11h /ethmac/tags/rel_3/
130 First draft of the Ethernet design document. Not a finished version. Still many
things missing.
mohor 6240d 12h /ethmac/tags/rel_3/
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
interfaces:
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 6240d 12h /ethmac/tags/rel_3/
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 6260d 11h /ethmac/tags/rel_3/
126 InvalidSymbol generation changed. mohor 6260d 11h /ethmac/tags/rel_3/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 6260d 11h /ethmac/tags/rel_3/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 6260d 12h /ethmac/tags/rel_3/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 6262d 13h /ethmac/tags/rel_3/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 6262d 13h /ethmac/tags/rel_3/
120 Unused files removed. mohor 6262d 14h /ethmac/tags/rel_3/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 6262d 14h /ethmac/tags/rel_3/
118 ShiftEnded synchronization changed. mohor 6266d 05h /ethmac/tags/rel_3/
117 Clock mrx_clk set to 2.5 MHz. mohor 6266d 15h /ethmac/tags/rel_3/
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 6266d 16h /ethmac/tags/rel_3/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 6267d 13h /ethmac/tags/rel_3/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 6268d 11h /ethmac/tags/rel_3/
113 RxPointer bug fixed. mohor 6275d 03h /ethmac/tags/rel_3/

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