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[/] [ethmac/] [tags/] [rel_4/] - Rev 23

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Rev	Log message	Author	Age	Path
23	Number of addresses (wb_adr_i) minimized.	mohor	8214d 20h	/ethmac/tags/rel_4/
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8214d 22h	/ethmac/tags/rel_4/
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8215d 19h	/ethmac/tags/rel_4/
20	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8239d 16h	/ethmac/tags/rel_4/
19	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8239d 16h	/ethmac/tags/rel_4/
18	Few little NCSIM warnings fixed.	mohor	8252d 17h	/ethmac/tags/rel_4/
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8279d 17h	/ethmac/tags/rel_4/
16	"else" was missing within the always block in file eth_wishbonedma.v.	mohor	8286d 23h	/ethmac/tags/rel_4/
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8288d 16h	/ethmac/tags/rel_4/
14	Unconnected signals are now connected.	mohor	8292d 22h	/ethmac/tags/rel_4/
13	New directory structure. Files upodated and put together.	mohor	8295d 06h	/ethmac/tags/rel_4/
12	Directory structure changed. Files checked and joind together.	mohor	8295d 09h	/ethmac/tags/rel_4/
11	Directory structure changed. Files checked and joind together.	mohor	8295d 10h	/ethmac/tags/rel_4/
10	Directory structure changed. Files checked and joind together.	mohor	8295d 10h	/ethmac/tags/rel_4/
9	Documentation updated to be synchronized to the verilog files.	mohor	8322d 18h	/ethmac/tags/rel_4/
8	Version 1.3. Status registers added. DMA channels 2 and 3 are not used any more. Things that are implementation specific were deleted out of the document.	mohor	8349d 23h	/ethmac/tags/rel_4/
7	Version 1.3. Status registers added. DMA channels 2 and 3 are not used any more. Things that are implementation specific were deleted out of the document.	mohor	8349d 23h	/ethmac/tags/rel_4/
6	no message	mohor	8349d 23h	/ethmac/tags/rel_4/
5	This is a Microsoft version of the spec in the pdf format.	mohor	8354d 08h	/ethmac/tags/rel_4/
4	deleted	mohor	8354d 08h	/ethmac/tags/rel_4/

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[/] [ethmac/] [tags/] [rel_4/] - Rev 23

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