OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_4/] [bench/] [verilog/] - Rev 338

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
338 root 3868d 11h /ethmac/tags/rel_4/bench/verilog/
335 New directory structure. root 3925d 16h /ethmac/tags/rel_4/bench/verilog/
151 This commit was manufactured by cvs2svn to create tag 'rel_4'. 6303d 07h /ethmac/tags/rel_4/bench/verilog/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 6344d 09h /ethmac/tags/rel_4/bench/verilog/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 6346d 09h /ethmac/tags/rel_4/bench/verilog/
117 Clock mrx_clk set to 2.5 MHz. mohor 6350d 12h /ethmac/tags/rel_4/bench/verilog/
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 6350d 12h /ethmac/tags/rel_4/bench/verilog/
108 Testbench supports unaligned accesses. mohor 6427d 15h /ethmac/tags/rel_4/bench/verilog/
107 TX_BUF_BASE changed. mohor 6427d 16h /ethmac/tags/rel_4/bench/verilog/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 6472d 13h /ethmac/tags/rel_4/bench/verilog/
80 Small fixes for external/internal DMA missmatches. mohor 6493d 09h /ethmac/tags/rel_4/bench/verilog/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 6503d 13h /ethmac/tags/rel_4/bench/verilog/
66 Testbench fixed, code simplified, unused signals removed. mohor 6503d 19h /ethmac/tags/rel_4/bench/verilog/
51 Added separate tests for Multicast, Unicast, Broadcast billditt 6505d 06h /ethmac/tags/rel_4/bench/verilog/
49 HASH0 and HASH1 register read/write added. mohor 6507d 05h /ethmac/tags/rel_4/bench/verilog/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 6513d 12h /ethmac/tags/rel_4/bench/verilog/
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 6573d 13h /ethmac/tags/rel_4/bench/verilog/
23 Number of addresses (wb_adr_i) minimized. mohor 6623d 14h /ethmac/tags/rel_4/bench/verilog/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 6623d 17h /ethmac/tags/rel_4/bench/verilog/
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 6648d 11h /ethmac/tags/rel_4/bench/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.