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[/] [ethmac/] [tags/] [rel_4/] [rtl/] [verilog/] [eth_top.v] - Rev 338

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Rev Log message Author Age Path
338 root 5463d 08h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
335 New directory structure. root 5520d 13h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
151 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7898d 04h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.		 mohor 7898d 04h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.		 mohor 7939d 05h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7947d 04h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8022d 13h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8033d 09h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.		 mohor 8061d 09h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
80 Small fixes for external/internal DMA missmatches. mohor 8088d 06h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
76 Interrupts changed in the top file mohor 8088d 07h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
70 Small fixes. mohor 8096d 12h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
68 Registered trimmed. Unused registers removed. mohor 8098d 09h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8098d 10h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
65 Testbench fixed, code simplified, unused signals removed. mohor 8098d 16h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
63 RxAbort is connected differently. mohor 8099d 09h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 8099d 11h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8100d 03h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.		 mohor 8102d 06h /ethmac/tags/rel_4/rtl/verilog/eth_top.v
43 Tx status is written back to the BD. mohor 8103d 14h /ethmac/tags/rel_4/rtl/verilog/eth_top.v

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