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[/] [ethmac/] [tags/] [rel_5/] - Rev 114

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Rev Log message Author Age Path
114 EXTERNAL_DMA removed. External DMA not supported. mohor 8114d 04h /ethmac/tags/rel_5/
113 RxPointer bug fixed. mohor 8120d 20h /ethmac/tags/rel_5/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8121d 09h /ethmac/tags/rel_5/
111 Master state machine had a bug when switching from master write to
master read.
mohor 8121d 23h /ethmac/tags/rel_5/
110 m_wb_cyc_o signal released after every single transfer. mohor 8122d 02h /ethmac/tags/rel_5/
109 Comment removed. mohor 8122d 02h /ethmac/tags/rel_5/
108 Testbench supports unaligned accesses. mohor 8189d 12h /ethmac/tags/rel_5/
107 TX_BUF_BASE changed. mohor 8189d 12h /ethmac/tags/rel_5/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8189d 12h /ethmac/tags/rel_5/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 8198d 14h /ethmac/tags/rel_5/
104 FCS should not be included in NibbleMinFl. mohor 8200d 08h /ethmac/tags/rel_5/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 8200d 08h /ethmac/tags/rel_5/
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 8200d 09h /ethmac/tags/rel_5/
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8200d 09h /ethmac/tags/rel_5/
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 8200d 09h /ethmac/tags/rel_5/
99 Document revised. mohor 8207d 07h /ethmac/tags/rel_5/
98 Document revised. mohor 8207d 08h /ethmac/tags/rel_5/
97 Small typo fixed. lampret 8224d 06h /ethmac/tags/rel_5/
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 8228d 06h /ethmac/tags/rel_5/
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 8228d 09h /ethmac/tags/rel_5/

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