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Rev Log message Author Age Path
188 PHY changed. tadej 7884d 14h /ethmac/tags/rel_5/
187 _info file added. mohor 7884d 14h /ethmac/tags/rel_5/
186 Macro for testbench (DO file). mohor 7884d 15h /ethmac/tags/rel_5/
185 Directory keeper. mohor 7884d 15h /ethmac/tags/rel_5/
184 Modelsim simulation environment should be ready now. mohor 7884d 15h /ethmac/tags/rel_5/
183 Modelsim environment added. mohor 7884d 16h /ethmac/tags/rel_5/
182 Full duplex test improved. tadej 7885d 16h /ethmac/tags/rel_5/
181 MIIM test look better. mohor 7885d 19h /ethmac/tags/rel_5/
180 Bench outputs data to display every 128 bytes. mohor 7888d 15h /ethmac/tags/rel_5/
179 Beautiful tests merget together mohor 7888d 15h /ethmac/tags/rel_5/
178 Rearanged testcases mohor 7888d 15h /ethmac/tags/rel_5/
177 Bug in MIIM fixed. mohor 7888d 19h /ethmac/tags/rel_5/
176 lists changed to new directory structure mohor 7888d 21h /ethmac/tags/rel_5/
175 Script fixed to new dir structure mohor 7888d 21h /ethmac/tags/rel_5/
174 Directory keeper mohor 7888d 21h /ethmac/tags/rel_5/
173 Keeps the directory mohor 7888d 21h /ethmac/tags/rel_5/
172 NCSIM simulation environment added to cvs mohor 7888d 21h /ethmac/tags/rel_5/
171 NCSIM simulation environment added. mohor 7888d 21h /ethmac/tags/rel_5/
170 Headers changed. mohor 7888d 21h /ethmac/tags/rel_5/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7888d 22h /ethmac/tags/rel_5/
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7889d 19h /ethmac/tags/rel_5/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7890d 20h /ethmac/tags/rel_5/
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7891d 20h /ethmac/tags/rel_5/
165 HASH improvement needed. mohor 7891d 23h /ethmac/tags/rel_5/
164 Ethernet debug registers removed. mohor 7891d 23h /ethmac/tags/rel_5/
163 Another temporary version. Core is almost finished. Testbench not included,
yet"		 mohor 7892d 15h /ethmac/tags/rel_5/
162 Another temporary version. Core is almost finished. Testbench not included,
yet.		 mohor 7892d 15h /ethmac/tags/rel_5/
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7892d 21h /ethmac/tags/rel_5/
160 error acknowledge cycle termination added to display. mohor 7892d 21h /ethmac/tags/rel_5/
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7893d 17h /ethmac/tags/rel_5/

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