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[/] [ethmac/] [tags/] [rel_5/] [rtl/] [verilog/] - Rev 338


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Rev Log message Author Age Path
338 root 4194d 08h /ethmac/tags/rel_5/rtl/verilog/
335 New directory structure. root 4251d 14h /ethmac/tags/rel_5/rtl/verilog/
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 6592d 08h /ethmac/tags/rel_5/rtl/verilog/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 6592d 08h /ethmac/tags/rel_5/rtl/verilog/
218 Typo error fixed. (When using Bist) mohor 6592d 10h /ethmac/tags/rel_5/rtl/verilog/
214 Signals for WISHBONE B3 compliant interface added. mohor 6593d 07h /ethmac/tags/rel_5/rtl/verilog/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6593d 07h /ethmac/tags/rel_5/rtl/verilog/
212 Minor $display change. mohor 6593d 07h /ethmac/tags/rel_5/rtl/verilog/
211 Bist added. mohor 6593d 07h /ethmac/tags/rel_5/rtl/verilog/
210 BIST added. mohor 6593d 07h /ethmac/tags/rel_5/rtl/verilog/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6610d 05h /ethmac/tags/rel_5/rtl/verilog/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
mohor 6610d 05h /ethmac/tags/rel_5/rtl/verilog/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 6613d 06h /ethmac/tags/rel_5/rtl/verilog/
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 6621d 09h /ethmac/tags/rel_5/rtl/verilog/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 6622d 09h /ethmac/tags/rel_5/rtl/verilog/
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 6623d 10h /ethmac/tags/rel_5/rtl/verilog/
165 HASH improvement needed. mohor 6623d 13h /ethmac/tags/rel_5/rtl/verilog/
164 Ethernet debug registers removed. mohor 6623d 13h /ethmac/tags/rel_5/rtl/verilog/
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 6624d 11h /ethmac/tags/rel_5/rtl/verilog/
160 error acknowledge cycle termination added to display. mohor 6624d 11h /ethmac/tags/rel_5/rtl/verilog/

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