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[/] [ethmac/] [tags/] [rel_5/] [rtl/] [verilog/] [eth_top.v] - Rev 338

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Rev Log message Author Age Path
338 root 5441d 19h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
335 New directory structure. root 5499d 01h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7839d 19h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
218 Typo error fixed. (When using Bist) mohor 7839d 21h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
214 Signals for WISHBONE B3 compliant interface added. mohor 7840d 18h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
210 BIST added. mohor 7840d 18h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7860d 17h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7868d 20h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
164 Ethernet debug registers removed. mohor 7871d 00h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 7871d 22h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.
mohor 7876d 16h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 7917d 16h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7925d 16h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8001d 00h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 8011d 20h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 8039d 21h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
80 Small fixes for external/internal DMA missmatches. mohor 8066d 18h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
76 Interrupts changed in the top file mohor 8066d 18h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
70 Small fixes. mohor 8075d 00h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
68 Registered trimmed. Unused registers removed. mohor 8076d 21h /ethmac/tags/rel_5/rtl/verilog/eth_top.v

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