OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_6/] [rtl/] - Rev 210

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
140 Syntax error fixed. mohor 7353d 11h /ethmac/tags/rel_6/rtl/
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 7353d 11h /ethmac/tags/rel_6/rtl/
138 Synchronous reset added. mohor 7353d 11h /ethmac/tags/rel_6/rtl/
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.
mohor 7353d 11h /ethmac/tags/rel_6/rtl/
136 Parameter ResetValue changed to capital letters. mohor 7353d 20h /ethmac/tags/rel_6/rtl/
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 7355d 13h /ethmac/tags/rel_6/rtl/
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).
mohor 7355d 14h /ethmac/tags/rel_6/rtl/
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7355d 14h /ethmac/tags/rel_6/rtl/
131 LinkFail signal was not latching appropriate bit. mohor 7355d 15h /ethmac/tags/rel_6/rtl/
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
interfaces:
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 7355d 16h /ethmac/tags/rel_6/rtl/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.