URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_6/] [rtl/] [verilog/] - Rev 338

Rev	Log message	Author	Age	Path
160	error acknowledge cycle termination added to display.	mohor	7892d 16h	/ethmac/tags/rel_6/rtl/verilog/
159	Async reset for WB_ACK_O removed (when core was in reset, it was impossible to access BDs). RxPointers and TxPointers names changed to be more descriptive. TxUnderRun synchronized.	mohor	7893d 13h	/ethmac/tags/rel_6/rtl/verilog/
150	Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal was not used OK.	mohor	7897d 10h	/ethmac/tags/rel_6/rtl/verilog/
149	Signals related to the control frames connected. Debug registers reg1, 2, 3, 4 connected.	mohor	7897d 10h	/ethmac/tags/rel_6/rtl/verilog/
148	Bug when last byte of destination address was not checked fixed.	mohor	7897d 10h	/ethmac/tags/rel_6/rtl/verilog/
147	ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to the control frames connected.	mohor	7897d 10h	/ethmac/tags/rel_6/rtl/verilog/
146	CarrierSenseLost status is not set when working in loopback mode.	mohor	7897d 10h	/ethmac/tags/rel_6/rtl/verilog/
145	Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).	mohor	7897d 10h	/ethmac/tags/rel_6/rtl/verilog/
143	Only values smaller or equal to 0x80 can be written to TX_BD_NUM register. r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.	mohor	7913d 13h	/ethmac/tags/rel_6/rtl/verilog/
141	Syntax error fixed.	mohor	7916d 07h	/ethmac/tags/rel_6/rtl/verilog/