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[/] [ethmac/] [tags/] [rel_7/] - Rev 221

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Rev Log message Author Age Path
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7195d 00h /ethmac/tags/rel_7
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7198d 01h /ethmac/tags/rel_7
218 Typo error fixed. (When using Bist) mohor 7198d 03h /ethmac/tags/rel_7
217 Bist supported. mohor 7198d 03h /ethmac/tags/rel_7
216 Bist signals added. mohor 7198d 03h /ethmac/tags/rel_7
215 Bist supported. mohor 7198d 03h /ethmac/tags/rel_7
214 Signals for WISHBONE B3 compliant interface added. mohor 7198d 23h /ethmac/tags/rel_7
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7198d 23h /ethmac/tags/rel_7
212 Minor $display change. mohor 7198d 23h /ethmac/tags/rel_7
211 Bist added. mohor 7199d 00h /ethmac/tags/rel_7
210 BIST added. mohor 7199d 00h /ethmac/tags/rel_7
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7200d 03h /ethmac/tags/rel_7
208 Virtual Silicon RAMs moved to lib directory tadej 7215d 21h /ethmac/tags/rel_7
207 Virtual Silicon RAM support fixed tadej 7215d 21h /ethmac/tags/rel_7
206 Virtual Silicon RAM added to the simulation. mohor 7215d 21h /ethmac/tags/rel_7
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7215d 22h /ethmac/tags/rel_7
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7215d 22h /ethmac/tags/rel_7
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 7215d 22h /ethmac/tags/rel_7
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7218d 23h /ethmac/tags/rel_7
201 Core size added to the document. mohor 7219d 00h /ethmac/tags/rel_7

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