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[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_fifo.v] - Rev 338

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Rev Log message Author Age Path
338 root 5441d 00h /ethmac/tags/rel_7/rtl/verilog/eth_fifo.v
335 New directory structure. root 5498d 05h /ethmac/tags/rel_7/rtl/verilog/eth_fifo.v
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7831d 22h /ethmac/tags/rel_7/rtl/verilog/eth_fifo.v
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 8011d 01h /ethmac/tags/rel_7/rtl/verilog/eth_fifo.v
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 8039d 01h /ethmac/tags/rel_7/rtl/verilog/eth_fifo.v
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.
mohor 8086d 22h /ethmac/tags/rel_7/rtl/verilog/eth_fifo.v

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