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[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_rxcounters.v] - Rev 338

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338 root 4893d 07h /ethmac/tags/rel_7/rtl/verilog/eth_rxcounters.v
335 New directory structure. root 4950d 13h /ethmac/tags/rel_7/rtl/verilog/eth_rxcounters.v
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7284d 06h /ethmac/tags/rel_7/rtl/verilog/eth_rxcounters.v
57 Format of the file changed a bit. mohor 7529d 12h /ethmac/tags/rel_7/rtl/verilog/eth_rxcounters.v
52 Modified for Address Checking,
addition of eth_addrcheck.v
billditt 7530d 02h /ethmac/tags/rel_7/rtl/verilog/eth_rxcounters.v
37 Link in the header changed. mohor 7552d 12h /ethmac/tags/rel_7/rtl/verilog/eth_rxcounters.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 7648d 14h /ethmac/tags/rel_7/rtl/verilog/eth_rxcounters.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 7722d 08h /ethmac/tags/rel_7/rtl/verilog/eth_rxcounters.v

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