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[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_top.v] - Rev 338


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Rev Log message Author Age Path
338 root 4893d 09h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
335 New directory structure. root 4950d 14h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7284d 07h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
227 Changed BIST scan signals. tadejm 7284d 07h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
218 Typo error fixed. (When using Bist) mohor 7291d 10h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
214 Signals for WISHBONE B3 compliant interface added. mohor 7292d 07h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
210 BIST added. mohor 7292d 07h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7312d 07h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7320d 09h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
164 Ethernet debug registers removed. mohor 7322d 13h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 7323d 11h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
mohor 7328d 05h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
mohor 7369d 06h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7377d 05h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 7452d 14h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 7463d 10h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 7491d 10h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
80 Small fixes for external/internal DMA missmatches. mohor 7518d 07h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
76 Interrupts changed in the top file mohor 7518d 08h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
70 Small fixes. mohor 7526d 13h /ethmac/tags/rel_7/rtl/verilog/eth_top.v

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