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Rev Log message Author Age Path
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 8089d 20h /ethmac/tags/rel_8/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 8092d 21h /ethmac/tags/rel_8/
218 Typo error fixed. (When using Bist) mohor 8092d 23h /ethmac/tags/rel_8/
217 Bist supported. mohor 8092d 23h /ethmac/tags/rel_8/
216 Bist signals added. mohor 8092d 23h /ethmac/tags/rel_8/
215 Bist supported. mohor 8093d 00h /ethmac/tags/rel_8/
214 Signals for WISHBONE B3 compliant interface added. mohor 8093d 20h /ethmac/tags/rel_8/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 8093d 20h /ethmac/tags/rel_8/
212 Minor $display change. mohor 8093d 20h /ethmac/tags/rel_8/
211 Bist added. mohor 8093d 20h /ethmac/tags/rel_8/
210 BIST added. mohor 8093d 20h /ethmac/tags/rel_8/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 8094d 23h /ethmac/tags/rel_8/
208 Virtual Silicon RAMs moved to lib directory tadej 8110d 17h /ethmac/tags/rel_8/
207 Virtual Silicon RAM support fixed tadej 8110d 17h /ethmac/tags/rel_8/
206 Virtual Silicon RAM added to the simulation. mohor 8110d 17h /ethmac/tags/rel_8/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 8110d 18h /ethmac/tags/rel_8/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 8110d 18h /ethmac/tags/rel_8/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 8110d 18h /ethmac/tags/rel_8/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 8113d 19h /ethmac/tags/rel_8/
201 Core size added to the document. mohor 8113d 20h /ethmac/tags/rel_8/

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