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Rev Log message Author Age Path
225 Some minor changes. tadejm 6668d 03h /ethmac/tags/rel_8/
224 Signals for a wave window in Modelsim. tadejm 6668d 04h /ethmac/tags/rel_8/
223 Some code changed due to bug fixes. tadejm 6668d 04h /ethmac/tags/rel_8/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6672d 02h /ethmac/tags/rel_8/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6675d 03h /ethmac/tags/rel_8/
218 Typo error fixed. (When using Bist) mohor 6675d 05h /ethmac/tags/rel_8/
217 Bist supported. mohor 6675d 05h /ethmac/tags/rel_8/
216 Bist signals added. mohor 6675d 05h /ethmac/tags/rel_8/
215 Bist supported. mohor 6675d 05h /ethmac/tags/rel_8/
214 Signals for WISHBONE B3 compliant interface added. mohor 6676d 01h /ethmac/tags/rel_8/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6676d 01h /ethmac/tags/rel_8/
212 Minor $display change. mohor 6676d 01h /ethmac/tags/rel_8/
211 Bist added. mohor 6676d 02h /ethmac/tags/rel_8/
210 BIST added. mohor 6676d 02h /ethmac/tags/rel_8/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6677d 05h /ethmac/tags/rel_8/
208 Virtual Silicon RAMs moved to lib directory tadej 6692d 23h /ethmac/tags/rel_8/
207 Virtual Silicon RAM support fixed tadej 6692d 23h /ethmac/tags/rel_8/
206 Virtual Silicon RAM added to the simulation. mohor 6692d 23h /ethmac/tags/rel_8/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 6693d 00h /ethmac/tags/rel_8/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6693d 00h /ethmac/tags/rel_8/

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