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Rev Log message Author Age Path
338 root 4153d 20h /ethmac/tags/rel_8/
335 New directory structure. root 4211d 01h /ethmac/tags/rel_8/
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 6544d 14h /ethmac/tags/rel_8/
229 case changed to casex. mohor 6544d 14h /ethmac/tags/rel_8/
227 Changed BIST scan signals. tadejm 6544d 18h /ethmac/tags/rel_8/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6544d 19h /ethmac/tags/rel_8/
225 Some minor changes. tadejm 6544d 20h /ethmac/tags/rel_8/
224 Signals for a wave window in Modelsim. tadejm 6544d 21h /ethmac/tags/rel_8/
223 Some code changed due to bug fixes. tadejm 6544d 21h /ethmac/tags/rel_8/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6548d 19h /ethmac/tags/rel_8/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6551d 20h /ethmac/tags/rel_8/
218 Typo error fixed. (When using Bist) mohor 6551d 22h /ethmac/tags/rel_8/
217 Bist supported. mohor 6551d 22h /ethmac/tags/rel_8/
216 Bist signals added. mohor 6551d 22h /ethmac/tags/rel_8/
215 Bist supported. mohor 6551d 22h /ethmac/tags/rel_8/
214 Signals for WISHBONE B3 compliant interface added. mohor 6552d 18h /ethmac/tags/rel_8/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6552d 18h /ethmac/tags/rel_8/
212 Minor $display change. mohor 6552d 18h /ethmac/tags/rel_8/
211 Bist added. mohor 6552d 19h /ethmac/tags/rel_8/
210 BIST added. mohor 6552d 19h /ethmac/tags/rel_8/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6553d 22h /ethmac/tags/rel_8/
208 Virtual Silicon RAMs moved to lib directory tadej 6569d 16h /ethmac/tags/rel_8/
207 Virtual Silicon RAM support fixed tadej 6569d 16h /ethmac/tags/rel_8/
206 Virtual Silicon RAM added to the simulation. mohor 6569d 16h /ethmac/tags/rel_8/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 6569d 17h /ethmac/tags/rel_8/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6569d 17h /ethmac/tags/rel_8/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 6569d 17h /ethmac/tags/rel_8/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 6572d 18h /ethmac/tags/rel_8/
201 Core size added to the document. mohor 6572d 19h /ethmac/tags/rel_8/
200 File with lower case checked in instead. mohor 6572d 19h /ethmac/tags/rel_8/

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