URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_9/] - Rev 158

Rev	Log message	Author	Age	Path
135	New revision. External DMA removed, TX_BD_NUM changed.	mohor	7923d 03h	/ethmac/tags/rel_9/
134	Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No need to multiply or devide any more.	mohor	7923d 04h	/ethmac/tags/rel_9/
133	- Busy signal was not set on time when scan status operation was performed and clock was divided with more than 2. - Nvalid remains valid two more clocks (was previously cleared too soon).	mohor	7923d 05h	/ethmac/tags/rel_9/
132	LinkFailRegister is reflecting the status of the PHY's link fail status bit.	mohor	7923d 06h	/ethmac/tags/rel_9/
131	LinkFail signal was not latching appropriate bit.	mohor	7923d 06h	/ethmac/tags/rel_9/
130	First draft of the Ethernet design document. Not a finished version. Still many things missing.	mohor	7923d 06h	/ethmac/tags/rel_9/
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	7923d 07h	/ethmac/tags/rel_9/
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7943d 06h	/ethmac/tags/rel_9/
126	InvalidSymbol generation changed.	mohor	7943d 06h	/ethmac/tags/rel_9/
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	7943d 06h	/ethmac/tags/rel_9/